The focus of the GT Network Processors group is to develop integrated host/NP systems that can deliver improved levels of cost/performance to end end users; support for innovative communication services; and hardware and software technologies for the implementation of active system area networks (ASANs). The use of the term "active" refers to the ability of the network interfaces to perform application-specific as well as system level computations in addition to their traditional role of data transfer.

This project adopts the view that the network infrastructure should be an active computational entity capable of supporting certain classes of computations which would otherwise be performed on the host CPUs. The result is a unique network-wide programming model where computations are dynamically placed within the host CPUs or the NPs depending upon the quality of service demands and network/CPU resource availabilities. The project seeks to demonstrate that such an approach is a better match for data intensive network-based applications and that the advent of programmable network processors, low-cost powerful embedded processors and configurable hardware makes such an approach economically viable and desirable.

The tangible project goals are:

• the demonstration of configurable network interfaces comprised of programmable network processors coupled with field programmable gate arrays (FPGAs) to implement data-intensive streaming computations during communication

• the use of the NPs' to effectively handle associated meta-information and perform computationally non-intensive operations best performed "close" to the network

• the movement of virtualization, scheduling and other QoS management functionality to the NPs and the use of the FPGAs to provide practical implementations of computationally demanding QoS scheduling disciplines for real-time communication

• the demonstration of an "extensible" software and quality management middleware layer that enables the dynamic placement of hardware (FPGA configurations) and software computations into the NPs and provides a uniform API to multiple heterogeneous network substrates. 

Several research components contribute to these goals:

• ViP: Virtualized multi-core Platforms - The project's goal is to develop hardware and software technologies to address performance, scalability and reliability in future, virtualized many-core platforms, particularly focusing on high-performance I/O and virtualized communication services and methods for virtualizing devices and accelerators, such as NICs, NPs, and FPGAs.
• Application-Programmable Routers and Interconnects - The project is concerned with the development of system- and IXP-level mechanisms and abstractions for mapping middleware- and application-level services to NPs, and a software architecture, SPLITS, to enable the joint use of combined host-IXP resources for efficient service execution.
• Intrusion Detection
• Compiler Support

Our approach is an experimental one driven by existing application implementations. The near term objective is the construction of an experimental testbed with off-the-shelf NI cards, including Myrinet and I2O boards in our previous work and IXP-2xxx routers used as communication co-processors in our current research. The experience with the testbed will be used in the design of a customized NI.

Acknowledgments

This research would not be possible without the generous support of our sponsors. We gratefully acknowledge the support of the National Science Foundation, the Department of Energy, Intel Corporation through its TE2000 and IXP architecture programs, and the Georgia Tech Research Corporation.
 

Useful links

• 3/28/2002: Rob Ibieta and Terri Durbin from the Intel Corporation visited to inaugurate the Intel IXA Laboratory.
• Old ASAN pages
• Georgia Tech internal Intel IXP pages