GIT-CERCS-06-12
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee,
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable 2D and 3D Microprocessors
Power delivery is a growing reliability concern in
microprocessors as the industry moves toward feature-rich,
power-hungrier designs. To battle the ever-aggravating power
consumption, modern microprocessor designers or researchers propose
and apply aggressive power-saving techniques in the form of
clock-gating and/or power-gating in order to operate the processor
within a given power envelope. However, these techniques often lead
to high-frequency current variations, which can stress the power
delivery system and jeopardize reliability due to inductive noise
(L di/dt) in the power supply network. In addition, with
the advent of 3D stacked IC technology that facilitates the design
of processors with much higher module density, the design of a low
impedance power-delivery network can be a daunting challenge. To
counteract these issues, modern microprocessors are designed to
operate under the worst-case current assumption by deploying
adequate decoupling capacitance. With the lowering of supply
voltages and increased leakage power and current consumption,
designing a processor for the worst case is becoming less appealing.
In this paper, we propose a new dynamic inductive-noise controlling
mechanism at the microarchitectural level that will limit the on-die
current demand within predefined bounds, regardless of the native
power and current characteristics of running applications. By
dynamically monitoring the access patterns of microarchitectural
modules, our mechanism can effectively limit simultaneous switching
activity of close-by modules, thereby leveling voltage ringing at
local power-pins. Compared to prior art, our di/dt controller is
the first that takes the processor's floorplan as well as its
power-pin distribution into account to provide a finer-grained
control with minimal performance degradation. Based on the
evaluation results using 2D and 3D floorplans, we
show that our techniques can significantly improve inductive noise
induced by current demand variation and reduce the average current
variability by up to 7 times with an average performance overhead of
4.0% (2D floorplan) and 3.8% (3D floorplan).