GIT-CERCS-04-37
Mongkol Ekpanyapong, Michael B. Healy, Chinnakrishnan S. Ballapuram, Sung Kyu
Lim, Hsien-Hsin S. Lee, Gabriel H. Loh,
Thermal-aware 3D Microarchitectural Floorplanning
Next generation deep submicron processor design will need
to take into consideration many performance limiting factors. Flip flops
are inserted in order to prevent global wire delay from becoming nonlinear,
enabling deeper pipelines and higher clock frequency. The move
to 3D ICs will also likely be used to further shorten wirelength. This
will cause thermal issues to become a major bottleneck to performance
improvement. In this paper we propose a floorplanning algorithm
which takes into consideration both thermal issues and profile weighted
wirelength using mathematical programming. Our profile-driven objective
improves performance by 20% over wirelength-driven. While the
thermal-driven objective improves temperature by 24% on average over
the profile-driven case.