GIT-CERCS-03-28
Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim,
Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor
Design
As process technology migrates to deep submicron with feature size
less than 100nm, global wire delay is becoming a major hindrance in
keeping the latency of intra-chip communication within a single cycle,
thus decaying the performance scalability substantially. An effective
floorplanning algorithm can no longer ignore the information of dynamic
communication patterns of applications. In this paper, using the profile
information acquired at the architecture/microarchitecture level, we
propose a "profile-guided microarchitectural floorplanner" that
considers both the impact of wire delay and the architectural behavior,
namely the inter-module communication, to reduce the latency of frequent
routes inside a processor and to maintain performance scalability.
Based on our simulation results, the profile-guided method shows a 5% to 40% IPC improvement when clock frequency is fixed. From the
perspective of instruction throughput (in BIPS), our floorplanner
is much more scalable than a conventional wire length based
floorplanner.