Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim,
Wire Congestion And Thermal Aware Global Placement For 3D VLSI Circuits
The recent popularity of 3D IC technology stems
from its enhanced performance capabilities and reduced wiring
length. However, wire congestion and thermal issues are exacerbated
due to the compact nature of these layered technologies.
In this paper, we develop techniques to reduce global the
temperature gradient and local and global congestions of 3D
circuit designs without compromising total intra-layer wirelength
or inter-layer via count. Our approach consists of two phases.
First, we use a multilevel min-cut based approach with a modified
gain function in order to minimize the local wire congestion
and power dissipation. Then, we perform simulated annealing
with a full-length thermal analysis to reduce the circuit's global
congestion and thermal gradient. Experimental results show that
when compared to the standard mincut approach, our thermal
gradient and local congestion are reduced by 25% each, global
congestion is reduced by over 7%. Moreover, we only see a 10%
increase in the wiring length and the number of vias required.